PWM configuration structure. More...
#include <bflb_pwm_v1.h>
Collaboration diagram for bflb_pwm_v1_channel_config_s:
Data Fields | |
| uint8_t | clk_source |
| uint16_t | clk_div |
| uint16_t | period |
Detailed Description
PWM configuration structure.
- Parameters
-
clk_source PWM clock source, use system clock definition clk_div PWM clock dividor, should be in 1~65535 period PWM period count, should be in 2~65535
Definition at line 79 of file bflb_pwm_v1.h.
Field Documentation
◆ clk_div
| uint16_t clk_div |
Definition at line 81 of file bflb_pwm_v1.h.
◆ clk_source
| uint8_t clk_source |
Definition at line 80 of file bflb_pwm_v1.h.
◆ period
| uint16_t period |
Definition at line 82 of file bflb_pwm_v1.h.
The documentation for this struct was generated from the following file:
- drivers/lhal/include/bflb_pwm_v1.h
