IR TX configuration structure. More...

#include <bflb_ir.h>

Collaboration diagram for bflb_ir_tx_config_s:

Data Fields
uint8_t	tx_mode

uint8_t	data_bits

uint8_t	tail_inverse

uint8_t	tail_enable

uint8_t	head_inverse

uint8_t	head_enable

uint8_t	logic1_inverse

uint8_t	logic0_inverse

uint8_t	data_enable

uint8_t	swm_enable

uint8_t	output_modulation

uint8_t	output_inverse

uint8_t	freerun_enable

uint8_t	continue_enable

uint8_t	fifo_width

uint8_t	fifo_threshold

uint8_t	logic0_pulse_width_1

uint8_t	logic0_pulse_width_0

uint8_t	logic1_pulse_width_1

uint8_t	logic1_pulse_width_0

uint8_t	head_pulse_width_1

uint8_t	head_pulse_width_0

uint8_t	tail_pulse_width_1

uint8_t	tail_pulse_width_0

uint8_t	modu_width_1

uint8_t	modu_width_0

uint16_t	pulse_width_unit

Detailed Description

IR TX configuration structure.

Parameters

tx_mode	TX mode select, use ir tx mode definition
data_bits	Bit count of data phase (don't care if tx freerun mode is enabled)
tail_inverse	Enable or disable signal of tail pulse inverse (don't care if SWM is enabled)
tail_enable	Enable or disable signal of tail pulse (don't care if SWM is enabled)
head_inverse	Enable or disable signal of head pulse inverse (don't care if SWM is enabled)
head_enable	Enable or disable signal of head pulse (don't care if SWM is enabled)
logic1_inverse	Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled)
logic0_inverse	Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled)
data_enable	Enable or disable signal of data pulse (don't care if SWM is enabled)
swm_enable	Enable or disable software mode(SWM)
output_modulation	Enable or disable signal of output modulation
output_inverse	Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high
freerun_enable	Enable or disable tx freerun mode (don't care if SWM is enabled)
continue_enable	Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no idle time between frames
fifo_width	IR frame size(also the valid width for each fifo entry), use ir tx fifo width valid width definition
fifo_threshold	TX FIFO threshold
logic0_pulse_width_1	Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled)
logic0_pulse_width_0	Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled)
logic1_pulse_width_1	Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled)
logic1_pulse_width_0	Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled)
head_pulse_width_1	Pulse width of head pulse phase 1 (don't care if SWM is enabled)
head_pulse_width_0	Pulse width of head pulse phase 0 (don't care if SWM is enabled)
tail_pulse_width_1	Pulse width of tail pulse phase 1 (don't care if SWM is enabled)
tail_pulse_width_0	Pulse width of tail pulse phase 0 (don't care if SWM is enabled)
modu_width_1	Modulation phase 1 width
modu_width_0	Modulation phase 0 width
pulse_width_unit	Pulse width unit

Definition at line 133 of file bflb_ir.h.

Field Documentation

◆ continue_enable

uint8_t continue_enable

Definition at line 147 of file bflb_ir.h.

◆ data_bits

uint8_t data_bits

Definition at line 135 of file bflb_ir.h.

◆ data_enable

uint8_t data_enable

Definition at line 142 of file bflb_ir.h.

◆ fifo_threshold

uint8_t fifo_threshold

Definition at line 149 of file bflb_ir.h.

◆ fifo_width

uint8_t fifo_width

Definition at line 148 of file bflb_ir.h.

◆ freerun_enable

uint8_t freerun_enable

Definition at line 146 of file bflb_ir.h.

◆ head_enable

uint8_t head_enable

Definition at line 139 of file bflb_ir.h.

◆ head_inverse

uint8_t head_inverse

Definition at line 138 of file bflb_ir.h.

◆ head_pulse_width_0

uint8_t head_pulse_width_0

Definition at line 155 of file bflb_ir.h.

◆ head_pulse_width_1

uint8_t head_pulse_width_1

Definition at line 154 of file bflb_ir.h.

◆ logic0_inverse

uint8_t logic0_inverse

Definition at line 141 of file bflb_ir.h.

◆ logic0_pulse_width_0

uint8_t logic0_pulse_width_0

Definition at line 151 of file bflb_ir.h.

◆ logic0_pulse_width_1

uint8_t logic0_pulse_width_1

Definition at line 150 of file bflb_ir.h.

◆ logic1_inverse

uint8_t logic1_inverse

Definition at line 140 of file bflb_ir.h.

◆ logic1_pulse_width_0

uint8_t logic1_pulse_width_0

Definition at line 153 of file bflb_ir.h.

◆ logic1_pulse_width_1

uint8_t logic1_pulse_width_1

Definition at line 152 of file bflb_ir.h.

◆ modu_width_0

uint8_t modu_width_0

Definition at line 159 of file bflb_ir.h.

◆ modu_width_1

uint8_t modu_width_1

Definition at line 158 of file bflb_ir.h.

◆ output_inverse

uint8_t output_inverse

Definition at line 145 of file bflb_ir.h.

◆ output_modulation

uint8_t output_modulation

Definition at line 144 of file bflb_ir.h.

◆ pulse_width_unit

uint16_t pulse_width_unit

Definition at line 160 of file bflb_ir.h.

◆ swm_enable

uint8_t swm_enable

Definition at line 143 of file bflb_ir.h.

◆ tail_enable

uint8_t tail_enable

Definition at line 137 of file bflb_ir.h.

◆ tail_inverse

uint8_t tail_inverse

Definition at line 136 of file bflb_ir.h.

◆ tail_pulse_width_0

uint8_t tail_pulse_width_0

Definition at line 157 of file bflb_ir.h.

◆ tail_pulse_width_1

uint8_t tail_pulse_width_1

Definition at line 156 of file bflb_ir.h.

◆ tx_mode

uint8_t tx_mode

Definition at line 134 of file bflb_ir.h.

The documentation for this struct was generated from the following file:

drivers/lhal/include/bflb_ir.h

Data Fields