17 #define DMA_MEMORY_TO_MEMORY 0 18 #define DMA_MEMORY_TO_PERIPH 1 19 #define DMA_PERIPH_TO_MEMORY 2 20 #define DMA_PERIPH_TO_PERIPH 3 28 #define DMA_ADDR_INCREMENT_DISABLE 0 29 #define DMA_ADDR_INCREMENT_ENABLE 1 37 #define DMA_DATA_WIDTH_8BIT 0 38 #define DMA_DATA_WIDTH_16BIT 1 39 #define DMA_DATA_WIDTH_32BIT 2 47 #define DMA_BURST_INCR1 0 48 #define DMA_BURST_INCR4 1 49 #define DMA_BURST_INCR8 2 50 #define DMA_BURST_INCR16 3 55 #if defined(BL702) || defined(BL602) || defined(BL702L) 59 #define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88) 60 #define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C) 62 #define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88) 63 #define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C) 65 #define DMA_ADDR_I2C0_TDR (0x4000A300 + 0x88) 66 #define DMA_ADDR_I2C0_RDR (0x4000A300 + 0x8C) 67 #define DMA_ADDR_SPI0_TDR (0x4000A200 + 0x88) 68 #define DMA_ADDR_SPI0_RDR (0x4000A200 + 0x8C) 70 #define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88) 71 #define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C) 73 #define DMA_ADDR_ADC_RDR (0x40002000 + 0x04) 75 #define DMA_ADDR_DAC_TDR (0x40002000 + 0x48) 78 #define DMA_ADDR_IR_TDR (0x4000A600 + 0x88) 79 #define DMA_ADDR_AUADC_RDR (0x4000AD00 + 0x88) 88 #define DMA_REQUEST_NONE 0x00000000 89 #define DMA_REQUEST_UART0_RX 0x00000000 90 #define DMA_REQUEST_UART0_TX 0x00000001 92 #define DMA_REQUEST_UART1_RX 0x00000002 93 #define DMA_REQUEST_UART1_TX 0x00000003 95 #define DMA_REQUEST_I2C0_RX 0x00000006 96 #define DMA_REQUEST_I2C0_TX 0x00000007 98 #define DMA_REQUEST_IR_TX 0x00000008 100 #define DMA_REQUEST_SPI0_RX 0x0000000A 101 #define DMA_REQUEST_SPI0_TX 0x0000000B 103 #define DMA_REQUEST_AUADC_RX 0x0000000D 106 #define DMA_REQUEST_I2S_RX 0x00000014 107 #define DMA_REQUEST_I2S_TX 0x00000015 109 #define DMA_REQUEST_ADC 0x00000016 111 #define DMA_REQUEST_DAC 0x00000017 121 #define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88) 122 #define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C) 123 #define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88) 124 #define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C) 125 #define DMA_ADDR_I2C0_TDR (0x2000A300 + 0x88) 126 #define DMA_ADDR_I2C0_RDR (0x2000A300 + 0x8C) 127 #define DMA_ADDR_SPI0_TDR (0x2000A200 + 0x88) 128 #define DMA_ADDR_SPI0_RDR (0x2000A200 + 0x8C) 129 #define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88) 130 #define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C) 131 #define DMA_ADDR_ADC_RDR (0x20002000 + 0x04) 132 #define DMA_ADDR_DAC_TDR (0x20002000 + 0x48) 133 #define DMA_ADDR_DBI_TDR (0x2000A800 + 0x88) 134 #define DMA_ADDR_AUDAC_TDR (0x20055000 + 0x94) 135 #define DMA_ADDR_AUADC_RDR (0x2000A000 + 0xC88) 136 #define DMA_ADDR_WO_TDR (0x20000000 + 0xB04) 144 #define DMA_REQUEST_NONE 0x00000000 145 #define DMA_REQUEST_UART0_RX 0x00000000 146 #define DMA_REQUEST_UART0_TX 0x00000001 147 #define DMA_REQUEST_UART1_RX 0x00000002 148 #define DMA_REQUEST_UART1_TX 0x00000003 149 #define DMA_REQUEST_I2C0_RX 0x00000006 150 #define DMA_REQUEST_I2C0_TX 0x00000007 151 #define DMA_REQUEST_WO 0x00000009 152 #define DMA_REQUEST_SPI0_RX 0x0000000A 153 #define DMA_REQUEST_SPI0_TX 0x0000000B 154 #define DMA_REQUEST_DBI_TX 0x00000014 155 #define DMA_REQUEST_AUADC_RX 0x00000015 156 #define DMA_REQUEST_AUDAC_TX 0x0000000D 157 #define DMA_REQUEST_I2S_RX 0x00000010 158 #define DMA_REQUEST_I2S_TX 0x00000011 159 #define DMA_REQUEST_ADC 0x00000016 160 #define DMA_REQUEST_DAC 0x00000017 166 #elif defined(BL808) || defined(BL606P) 170 #define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88) 171 #define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C) 172 #define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88) 173 #define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C) 174 #define DMA_ADDR_UART2_TDR (0x2000AA00 + 0x88) 175 #define DMA_ADDR_UART2_RDR (0x2000AA00 + 0x8C) 176 #define DMA_ADDR_UART3_TDR (0x30002000 + 0x88) 177 #define DMA_ADDR_UART3_RDR (0x30002000 + 0x8C) 178 #define DMA_ADDR_I2C0_TDR (0x2000A300 + 0x88) 179 #define DMA_ADDR_I2C0_RDR (0x2000A300 + 0x8C) 180 #define DMA_ADDR_I2C1_TDR (0x2000A900 + 0x88) 181 #define DMA_ADDR_I2C1_RDR (0x2000A900 + 0x8C) 182 #define DMA_ADDR_I2C2_TDR (0x30003000 + 0x88) 183 #define DMA_ADDR_I2C2_RDR (0x30003000 + 0x8C) 184 #define DMA_ADDR_I2C3_TDR (0x30004000 + 0x88) 185 #define DMA_ADDR_I2C3_RDR (0x30004000 + 0x8C) 186 #define DMA_ADDR_SPI0_TDR (0x2000A200 + 0x88) 187 #define DMA_ADDR_SPI0_RDR (0x2000A200 + 0x8C) 188 #define DMA_ADDR_SPI1_TDR (0x30008000 + 0x88) 189 #define DMA_ADDR_SPI1_RDR (0x30008000 + 0x8C) 190 #define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88) 191 #define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C) 192 #define DMA_ADDR_ADC_RDR (0x20002000 + 0x04) 193 #define DMA_ADDR_DAC_TDR (0x20002000 + 0x48) 194 #define DMA_ADDR_IR_TDR (0x2000A600 + 0x88) 195 #define DMA_ADDR_WO_TDR (0x20000000 + 0xB04) 203 #define DMA_REQUEST_NONE 0x00000000 204 #define DMA_REQUEST_UART0_RX 0x00000000 205 #define DMA_REQUEST_UART0_TX 0x00000001 206 #define DMA_REQUEST_UART1_RX 0x00000002 207 #define DMA_REQUEST_UART1_TX 0x00000003 208 #define DMA_REQUEST_UART2_RX 0x00000004 209 #define DMA_REQUEST_UART2_TX 0x00000005 210 #define DMA_REQUEST_I2C0_RX 0x00000006 211 #define DMA_REQUEST_I2C0_TX 0x00000007 212 #define DMA_REQUEST_IR_TX 0x00000008 213 #define DMA_REQUEST_WO 0x00000009 214 #define DMA_REQUEST_SPI0_RX 0x0000000A 215 #define DMA_REQUEST_SPI0_TX 0x0000000B 216 #define DMA_REQUEST_AUDIO_RX 0x0000000C 217 #define DMA_REQUEST_AUDIO_TX 0x0000000D 218 #define DMA_REQUEST_I2C1_RX 0x0000000E 219 #define DMA_REQUEST_I2C1_TX 0x0000000F 220 #define DMA_REQUEST_I2S_RX 0x00000010 221 #define DMA_REQUEST_I2S_TX 0x00000011 222 #define DMA_REQUEST_ADC 0x00000016 223 #define DMA_REQUEST_DAC 0x00000017 226 #define DMA_REQUEST_UART3_RX 0x00000000 227 #define DMA_REQUEST_UART3_TX 0x00000001 228 #define DMA_REQUEST_SPI1_RX 0x00000002 229 #define DMA_REQUEST_SPI1_TX 0x00000003 230 #define DMA_REQUEST_I2C2_RX 0x00000006 231 #define DMA_REQUEST_I2C2_TX 0x00000007 232 #define DMA_REQUEST_I2C3_RX 0x00000008 233 #define DMA_REQUEST_I2C3_TX 0x00000009 242 #define DMA_ADDR_UART0_TDR (0x20010000 + 0x88) 243 #define DMA_ADDR_UART0_RDR (0x20010000 + 0x8C) 244 #define DMA_ADDR_UART1_TDR (0x20011000 + 0x88) 245 #define DMA_ADDR_UART1_RDR (0x20011000 + 0x8C) 246 #define DMA_ADDR_UART2_TDR (0x20012000 + 0x88) 247 #define DMA_ADDR_UART2_RDR (0x20012000 + 0x8C) 248 #define DMA_ADDR_I2C0_TDR (0x20014000 + 0x88) 249 #define DMA_ADDR_I2C0_RDR (0x20014000 + 0x8C) 250 #define DMA_ADDR_I2C1_TDR (0x20015000 + 0x88) 251 #define DMA_ADDR_I2C1_RDR (0x20015000 + 0x8C) 252 #define DMA_ADDR_SPI0_TDR (0x20018000 + 0x88) 253 #define DMA_ADDR_SPI0_RDR (0x20018000 + 0x8C) 254 #define DMA_ADDR_I2S_TDR (0x2001E000 + 0x88) 255 #define DMA_ADDR_I2S_RDR (0x2001E000 + 0x8C) 256 #define DMA_ADDR_ADC_RDR (0x20002000 + 0x04) 257 #define DMA_ADDR_DAC_TDR (0x20002000 + 0x48) 265 #define DMA_REQUEST_NONE 0x00000000 266 #define DMA_REQUEST_UART0_RX 0x00000000 267 #define DMA_REQUEST_UART0_TX 0x00000001 268 #define DMA_REQUEST_UART1_RX 0x00000002 269 #define DMA_REQUEST_UART1_TX 0x00000003 270 #define DMA_REQUEST_UART2_RX 0x00000004 271 #define DMA_REQUEST_UART2_TX 0x00000005 272 #define DMA_REQUEST_I2C0_RX 0x00000006 273 #define DMA_REQUEST_I2C0_TX 0x00000007 274 #define DMA_REQUEST_I2C1_RX 0x00000008 275 #define DMA_REQUEST_I2C1_TX 0x00000009 276 #define DMA_REQUEST_SPI0_RX 0x0000000A 277 #define DMA_REQUEST_SPI0_TX 0x0000000B 278 #define DMA_REQUEST_I2S_RX 0x00000010 279 #define DMA_REQUEST_I2S_TX 0x00000011 280 #define DMA_REQUEST_ADC 0x00000016 281 #define DMA_REQUEST_DAC 0x00000017 291 #define DMA_CMD_SET_SRCADDR_INCREMENT (0x01) 292 #define DMA_CMD_SET_DSTADDR_INCREMENT (0x02) 293 #define DMA_CMD_SET_ADD_MODE (0x03) 294 #define DMA_CMD_SET_REDUCE_MODE (0x04) 295 #define DMA_CMD_SET_LLI_CONFIG (0x05) 296 #define DMA_CMD_GET_LLI_SRCADDR (0x06) 297 #define DMA_CMD_GET_LLI_DSTADDR (0x07) 298 #define DMA_CMD_GET_LLI_CONTROL (0x08) 299 #define DMA_CMD_GET_LLI_COUNT (0x09) 385 void (*copy)(uint8_t *data, uint32_t len);
468 uint32_t used_lli_count);
485 uint8_t rx_llipool_size,
488 uint32_t dst_buf_size,
489 void (*copy)(uint8_t *data, uint32_t len));
bool bflb_dma_channel_isbusy(struct bflb_device_s *dev)
Check if dma channel is in busy.
uint32_t dma_last_lli_count
bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev)
Check if dma channel transfers completely.
int bflb_dma_channel_lli_reload(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count, struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count)
Config dma channel lli.
void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t used_lli_count)
Enable lli continueous mode.
void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_channel_config_s *config)
Initialize dma channel.
void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev)
Clear dma channel transmission completion interrupt status.
void bflb_dma_channel_deinit(struct bflb_device_s *dev)
Deinitialize dma channel.
void bflb_dma_channel_stop(struct bflb_device_s *dev)
Stop dma channel transfer.
DMA channel lli pool structure.
void bflb_dma_channel_start(struct bflb_device_s *dev)
Start dma channel transfer.
struct bflb_dma_lli_control_s::@0 bits
struct bflb_device_s * dma_ch
void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask)
Enable or disable dma channel transmission completion interrupt.
DMA configuration structure.
DMA channel lli transfer structure.
void bflb_dma_channel_irq_attach(struct bflb_device_s *dev, void(*callback)(void *arg), void *arg)
Register dma channel transmission completion interrupt callback.
void bflb_rx_cycle_dma_init(struct bflb_rx_cycle_dma *rx_dma, struct bflb_device_s *dma_ch, struct bflb_dma_channel_lli_pool_s *rx_llipool, uint8_t rx_llipool_size, uint32_t src_addr, uint8_t *dst_buf, uint32_t dst_buf_size, void(*copy)(uint8_t *data, uint32_t len))
Init rx cycle dma.
void bflb_rx_cycle_dma_process(struct bflb_rx_cycle_dma *rx_dma, bool in_dma_isr)
Rx cycle dma process.
int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
Control dma feature.
void bflb_dma_channel_irq_detach(struct bflb_device_s *dev)
Unregister dma channel transmission completion interrupt callback.