17 #define BFLB_SYSTEM_ROOT_CLOCK 0 18 #define BFLB_SYSTEM_CPU_CLK 1 19 #define BFLB_SYSTEM_PBCLK 2 20 #define BFLB_SYSTEM_XCLK 3 21 #define BFLB_SYSTEM_32K_CLK 4 26 #if defined(BL702) || defined(BL602) || defined(BL702L) 27 #define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24) 28 #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 29 #define BFLB_GLB_CGEN1_BASE (0x20000000 + 0x584) 30 #define BFLB_GLB_CGEN2_BASE (0x20000000 + 0x588) 33 #define PERIPHERAL_CLOCK_ADC_DAC_ENABLE() \ 35 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 37 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 40 #define PERIPHERAL_CLOCK_SEC_ENABLE() \ 42 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 44 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 47 #define PERIPHERAL_CLOCK_DMA0_ENABLE() \ 49 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 50 regval |= (1 << 12); \ 51 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 54 #if defined(BL606P) || defined(BL808) 55 #define PERIPHERAL_CLOCK_DMA1_ENABLE() 56 #define PERIPHERAL_CLOCK_DMA2_ENABLE() 59 #define PERIPHERAL_CLOCK_UART0_ENABLE() \ 61 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 62 regval |= (1 << 16); \ 63 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 66 #define PERIPHERAL_CLOCK_UART1_ENABLE() \ 68 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 69 regval |= (1 << 17); \ 70 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 73 #if defined(BL606P) || defined(BL808) || defined(BL628) 74 #define PERIPHERAL_CLOCK_UART2_ENABLE() 77 #if defined(BL606P) || defined(BL808) 78 #define PERIPHERAL_CLOCK_SPI0_1_ENABLE() \ 80 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 81 regval |= (1 << 18); \ 82 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 85 #define PERIPHERAL_CLOCK_SPI0_ENABLE() \ 87 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 88 regval |= (1 << 18); \ 89 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 93 #define PERIPHERAL_CLOCK_I2C0_ENABLE() \ 95 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 96 regval |= (1 << 19); \ 97 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 100 #if defined(BL606P) || defined(BL808) || defined(BL616) || defined(BL628) 101 #define PERIPHERAL_CLOCK_I2C1_ENABLE() \ 103 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 104 regval |= (1 << 25); \ 105 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 110 #define PERIPHERAL_CLOCK_PWM0_ENABLE() \ 112 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 113 regval |= (1 << 20); \ 114 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 117 #define PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE() \ 119 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 120 regval |= (1 << 21); \ 121 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 124 #define PERIPHERAL_CLOCK_IR_ENABLE() \ 126 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 127 regval |= (1 << 22); \ 128 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 131 #define PERIPHERAL_CLOCK_CKS_ENABLE() \ 133 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 134 regval |= (1 << 23); \ 135 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 138 #if defined(BL606P) || defined(BL808) 139 #define PERIPHERAL_CLOCK_CAN_UART2_ENABLE() \ 141 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 142 regval |= (1 << 26); \ 143 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 145 #elif defined(BL616) || defined(BL628) 146 #define PERIPHERAL_CLOCK_CAN_ENABLE() \ 148 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 149 regval |= (1 << 26); \ 150 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 155 #define PERIPHERAL_CLOCK_USB_ENABLE() \ 157 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 158 regval |= (1 << 28); \ 159 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 162 #define PERIPHERAL_CLOCK_I2S_ENABLE() \ 164 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 165 regval |= (1 << 26); \ 166 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 169 #elif defined(BL616) || defined(BL606P) || defined(BL808) 170 #define PERIPHERAL_CLOCK_USB_ENABLE() \ 172 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 173 regval |= (1 << 13); \ 174 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 177 #define PERIPHERAL_CLOCK_I2S_ENABLE() \ 179 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 180 regval |= (1 << 27); \ 181 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 186 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) 187 #define PERIPHERAL_CLOCK_SDH_ENABLE() \ 189 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \ 190 regval |= (1 << 22); \ 191 putreg32(regval, BFLB_GLB_CGEN2_BASE); \ 196 #define PERIPHERAL_CLOCK_EMAC_ENABLE() \ 198 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \ 199 regval |= (1 << 13); \ 200 putreg32(regval, BFLB_GLB_CGEN1_BASE); \ 202 #elif defined(BL616) || defined(BL606P) || defined(BL808) 203 #define PERIPHERAL_CLOCK_EMAC_ENABLE() \ 205 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \ 206 regval |= (1 << 23); \ 207 putreg32(regval, BFLB_GLB_CGEN2_BASE); \ 212 #define PERIPHERAL_CLOCK_AUDIO_ENABLE() \ 214 volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \ 215 regval |= (1 << 21); \ 216 putreg32(regval, BFLB_GLB_CGEN2_BASE); \ uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
Get peripheral clock frequence.
uint32_t bflb_clk_get_system_clock(uint8_t type)
Get system clock frequence.