Bouffalo SDK  1.0
Bouffalolab Software Development Kit
bflb_clock.h
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1 #ifndef _BFLB_CLOCK_H
2 #define _BFLB_CLOCK_H
3 
4 #include "bflb_core.h"
5 
17 #define BFLB_SYSTEM_ROOT_CLOCK 0
18 #define BFLB_SYSTEM_CPU_CLK 1
19 #define BFLB_SYSTEM_PBCLK 2
20 #define BFLB_SYSTEM_XCLK 3
21 #define BFLB_SYSTEM_32K_CLK 4
22 
26 #if defined(BL702) || defined(BL602) || defined(BL702L)
27 #define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24)
28 #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
29 #define BFLB_GLB_CGEN1_BASE (0x20000000 + 0x584)
30 #define BFLB_GLB_CGEN2_BASE (0x20000000 + 0x588)
31 #endif
32 
33 #define PERIPHERAL_CLOCK_ADC_DAC_ENABLE() \
34  do { \
35  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
36  regval |= (1 << 2); \
37  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
38  } while (0)
39 
40 #define PERIPHERAL_CLOCK_SEC_ENABLE() \
41  do { \
42  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
43  regval |= (1 << 4); \
44  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
45  } while (0)
46 
47 #define PERIPHERAL_CLOCK_DMA0_ENABLE() \
48  do { \
49  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
50  regval |= (1 << 12); \
51  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
52  } while (0)
53 
54 #if defined(BL606P) || defined(BL808)
55 #define PERIPHERAL_CLOCK_DMA1_ENABLE()
56 #define PERIPHERAL_CLOCK_DMA2_ENABLE()
57 #endif
58 
59 #define PERIPHERAL_CLOCK_UART0_ENABLE() \
60  do { \
61  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
62  regval |= (1 << 16); \
63  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
64  } while (0)
65 
66 #define PERIPHERAL_CLOCK_UART1_ENABLE() \
67  do { \
68  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
69  regval |= (1 << 17); \
70  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
71  } while (0)
72 
73 #if defined(BL606P) || defined(BL808) || defined(BL628)
74 #define PERIPHERAL_CLOCK_UART2_ENABLE()
75 #endif
76 
77 #if defined(BL606P) || defined(BL808)
78 #define PERIPHERAL_CLOCK_SPI0_1_ENABLE() \
79  do { \
80  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
81  regval |= (1 << 18); \
82  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
83  } while (0)
84 #else
85 #define PERIPHERAL_CLOCK_SPI0_ENABLE() \
86  do { \
87  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
88  regval |= (1 << 18); \
89  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
90  } while (0)
91 #endif
92 
93 #define PERIPHERAL_CLOCK_I2C0_ENABLE() \
94  do { \
95  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
96  regval |= (1 << 19); \
97  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
98  } while (0)
99 
100 #if defined(BL606P) || defined(BL808) || defined(BL616) || defined(BL628)
101 #define PERIPHERAL_CLOCK_I2C1_ENABLE() \
102  do { \
103  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
104  regval |= (1 << 25); \
105  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
106  } while (0)
107 
108 #endif
109 
110 #define PERIPHERAL_CLOCK_PWM0_ENABLE() \
111  do { \
112  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
113  regval |= (1 << 20); \
114  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
115  } while (0)
116 
117 #define PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE() \
118  do { \
119  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
120  regval |= (1 << 21); \
121  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
122  } while (0)
123 
124 #define PERIPHERAL_CLOCK_IR_ENABLE() \
125  do { \
126  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
127  regval |= (1 << 22); \
128  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
129  } while (0)
130 
131 #define PERIPHERAL_CLOCK_CKS_ENABLE() \
132  do { \
133  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
134  regval |= (1 << 23); \
135  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
136  } while (0)
137 
138 #if defined(BL606P) || defined(BL808)
139 #define PERIPHERAL_CLOCK_CAN_UART2_ENABLE() \
140  do { \
141  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
142  regval |= (1 << 26); \
143  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
144  } while (0)
145 #elif defined(BL616) || defined(BL628)
146 #define PERIPHERAL_CLOCK_CAN_ENABLE() \
147  do { \
148  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
149  regval |= (1 << 26); \
150  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
151  } while (0)
152 #endif
153 
154 #if defined(BL702)
155 #define PERIPHERAL_CLOCK_USB_ENABLE() \
156  do { \
157  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
158  regval |= (1 << 28); \
159  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
160  } while (0)
161 
162 #define PERIPHERAL_CLOCK_I2S_ENABLE() \
163  do { \
164  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
165  regval |= (1 << 26); \
166  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
167  } while (0)
168 
169 #elif defined(BL616) || defined(BL606P) || defined(BL808)
170 #define PERIPHERAL_CLOCK_USB_ENABLE() \
171  do { \
172  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
173  regval |= (1 << 13); \
174  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
175  } while (0)
176 
177 #define PERIPHERAL_CLOCK_I2S_ENABLE() \
178  do { \
179  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
180  regval |= (1 << 27); \
181  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
182  } while (0)
183 
184 #endif
185 
186 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
187 #define PERIPHERAL_CLOCK_SDH_ENABLE() \
188  do { \
189  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
190  regval |= (1 << 22); \
191  putreg32(regval, BFLB_GLB_CGEN2_BASE); \
192  } while (0)
193 #endif
194 
195 #if defined(BL702)
196 #define PERIPHERAL_CLOCK_EMAC_ENABLE() \
197  do { \
198  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
199  regval |= (1 << 13); \
200  putreg32(regval, BFLB_GLB_CGEN1_BASE); \
201  } while (0)
202 #elif defined(BL616) || defined(BL606P) || defined(BL808)
203 #define PERIPHERAL_CLOCK_EMAC_ENABLE() \
204  do { \
205  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
206  regval |= (1 << 23); \
207  putreg32(regval, BFLB_GLB_CGEN2_BASE); \
208  } while (0)
209 #endif
210 
211 #if defined(BL616)
212 #define PERIPHERAL_CLOCK_AUDIO_ENABLE() \
213  do { \
214  volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
215  regval |= (1 << 21); \
216  putreg32(regval, BFLB_GLB_CGEN2_BASE); \
217  } while (0)
218 #endif
219 
220 #ifdef __cplusplus
221 extern "C" {
222 #endif
223 
230 uint32_t bflb_clk_get_system_clock(uint8_t type);
231 
239 uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx);
240 
241 #ifdef __cplusplus
242 }
243 #endif
244 
253 #endif
uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
Get peripheral clock frequence.
uint32_t bflb_clk_get_system_clock(uint8_t type)
Get system clock frequence.