14 #define EMAC_DO_FLUSH_DATA (1) 17 #define EMAC_CLK_USE_EXTERNAL (0) 18 #define EMAC_CLK_USE_INTERNAL (1) 23 #define EMAC_CMD_NO_PREAMBLE_MODE (0x01) 24 #define EMAC_CMD_EN_PROMISCUOUS (0x02) 25 #define EMAC_CMD_FRAME_GAP_CHECK (0x03) 26 #define EMAC_CMD_FULL_DUPLEX (0x04) 27 #define EMAC_CMD_EN_TX_CRC_FIELD (0x05) 28 #define EMAC_CMD_RECV_HUGE_FRAMES (0x06) 29 #define EMAC_CMD_EN_AUTO_PADDING (0x07) 30 #define EMAC_CMD_RECV_SMALL_FRAME (0x08) 31 #define EMAC_CMD_SET_PHY_ADDRESS (0x09) 32 #define EMAC_CMD_SET_MAC_ADDRESS (0x0A) 33 #define EMAC_CMD_SET_PACKET_GAP (0x0B) 34 #define EMAC_CMD_SET_MIN_FRAME (0x0C) 35 #define EMAC_CMD_SET_MAX_FRAME (0x0D) 36 #define EMAC_CMD_SET_MAXRET (0x0E) 37 #define EMAC_CMD_SET_COLLVALID (0x0F) 45 #define PHY_STATE_DOWN (0) 46 #define PHY_STATE_READY (1) 47 #define PHY_STATE_UP (2) 48 #define PHY_STATE_RUNNING (3) 49 #define PHY_STATE_NOLINK (4) 50 #define PHY_STATE_STOPPED (5) 51 #define PHY_STATE_TESTING (6) 57 #define EMAC_NORMAL_PACKET (uint32_t)(0) 58 #define EMAC_FRAGMENT_PACKET (uint32_t)(0x01) 59 #define EMAC_NOCOPY_PACKET (uint32_t)(0x02) 64 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) 65 #define ETH_HEADER_SZIE ((uint32_t)14U) 66 #define ETH_CRC_SIZE ((uint32_t)4U) 67 #define ETH_EXTRA_SIZE ((uint32_t)2U) 68 #define ETH_VLAN_TAG_SIZE ((uint32_t)4U) 69 #define ETH_MIN_ETH_PAYLOAD_SIZE ((uint32_t)46U) 70 #define ETH_MAX_ETH_PAYLOAD_SIZE ((uint32_t)1500U) 71 #define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) 74 #ifndef ETH_TX_BUFFER_SIZE 75 #define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) 77 #ifndef ETH_RX_BUFFER_SIZE 78 #define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) 82 #define EMAC_INT_EN_TX_DONE (1 << 0) 83 #define EMAC_INT_EN_TX_ERROR (1 << 1) 84 #define EMAC_INT_EN_RX_DONE (1 << 2) 85 #define EMAC_INT_EN_RX_ERROR (1 << 3) 86 #define EMAC_INT_EN_RX_BUSY (1 << 4) 87 #define EMAC_INT_EN_TX_CTRL (1 << 5) 88 #define EMAC_INT_EN_RX_CTRL (1 << 6) 89 #define EMAC_INT_EN_ALL (0x7f << 0) 92 #define EMAC_INT_STS_TX_DONE (1 << 0) 93 #define EMAC_INT_STS_TX_ERROR (1 << 1) 94 #define EMAC_INT_STS_RX_DONE (1 << 2) 95 #define EMAC_INT_STS_RX_ERROR (1 << 3) 96 #define EMAC_INT_STS_RX_BUSY (1 << 4) 97 #define EMAC_INT_STS_TX_CTRL (1 << 5) 98 #define EMAC_INT_STS_RX_CTRL (1 << 6) 99 #define EMAC_INT_STS_ALL (0x7f << 0) 102 #define EMAC_BD_TYPE_INVLAID (0) 103 #define EMAC_BD_TYPE_TX (1) 104 #define EMAC_BD_TYPE_RX (2) 105 #define EMAC_BD_TYPE_NONE (3) 106 #define EMAC_BD_TYPE_MAX (0x7FFFFFFF) void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable)
void bflb_emac_init(struct bflb_device_s *dev, const struct bflb_emac_config_s *config)
EMAC configuration structure.
void bflb_emac_stop_tx(struct bflb_device_s *dev)
void bflb_emac_bd_tx_dequeue(uint32_t index)
void bflb_emac_stop_rx(struct bflb_device_s *dev)
void bflb_emac_start_rx(struct bflb_device_s *dev)
int emac_bd_fragment_support(void)
void bflb_emac_stop(struct bflb_device_s *dev)
int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out)
void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag)
int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
void bflb_emac_bd_rx_enqueue(uint32_t index)
int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val)
void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count)
EMAC phy configuration structure.
void bflb_emac_start_tx(struct bflb_device_s *dev)
void bflb_emac_bd_tx_on_err(uint32_t index)
void bflb_emac_bd_rx_on_err(uint32_t index)
int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev)
uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt)
int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val)
void bflb_emac_start(struct bflb_device_s *dev)